1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, such as an LSI, and particularly to a semiconductor integrated circuit in which a scan circuit is provided, and to a method of testing the same.
2. Description of the Related Art
Scan testing has conventionally been known as a method of testing LSIs.
FIG. 4 shows a model of a semiconductor integrated circuit (LSI) on which scan testing can be performed. Various logical circuits are constructed as internal circuitry 60 in this LSI, and input data from, for example, input terminals in 1 through in 4 are computed by the internal circuitry 60. Then, the computed result is outputted from output terminals out 1 through out 4.
In such an LSI, in order to make scan testing possible, scan flip-flops (hereinafter referred to as FFs) 61 through 68 are provided as shown in the figure. These scan FFs 61 through 68 are, for example, flip-flops having the functions of a multiplexer, and a given required number of scan flip-flops are serially connected between a scan input terminal (scan in) and a scan output terminal (scan out). This serial connection is called a scan chain.
By inputting a scan data pattern from the scan input terminal (scan in), the scan flip-flops 61 through 64 are set to arbitrary values as input for the internal circuitry 60. The values that are set are processed by the internal circuitry 60, and result data thereof are outputted to the scan flip-flops 65 through 68. Then, data on the scan chain are shifted, and the result data outputted from the scan output terminal (scan out) are checked. Through such a method, LSIs are tested for defects.
FIG. 4 shows an extremely simplified model of scan testing. Various scan testing methods are described in, for example, the documents below.
[Patent Document 1] Japanese Patent Application Publication Sho-63-134970
[Patent Document 2] Japanese Patent Application Publication Hei-4-72583
[Patent Document 3] Japanese Patent Application Publication Hei-5-172897
[Patent Document 4] Japanese Patent Application Publication Hei-4-287510